Since a high reliability computer system, of which a storage device is representative, can be continually operated for 24 hours per day and 365 days per year, accordingly such a system is endowed with a plurality of functions for detecting any fault in the hardware which is used internally to the storage device at an early stage, in order to ensure that the storage device operates stably. For example, in relation to an LSI which performs data transfer internally in the storage device, it is known for an MPU to execute a diagnosis program for this LSI, and for a micro diagnosis function to diagnose internal faults of this LSI. It is a popular method for diagnosing an LSI that the LSI is connected to an external diagnosis device, which detects any faults in the LSI, in a manufacturing process of the LSI. The above-mentioned micro diagnosis has its advantage in that detecting faults can be performed while the storage device is working, since the MPU diagnoses the LSI using a program.
Nowadays, in the design technology for LSIs, RTL (Register Transfer Level) design is mainstream. RTL is a degree of logical abstraction of the LSI. In RTL, a so called hardware description language (HDL) such as VHDL or Verilog-HDL is used as a programming language, and the flow of data is described for each register to register as a unit. And, by using so called logic synthesis tool software, source code in an HDL which is described at RTL is automatically converted to a so called GATE level net list circuit diagram, in which IC cells are connected one another.
However, in recent years, due to increase of the scale of semiconductor integration and increase of the complication of design specifications, the amount of design work per each individual designer has increased, and, in RTL design, the design task has come to occupy a very great period of time, so that it has become difficult to ensure the required quality of design.
In response to this type of situation, in recent years, methods have started to be employed for raising the level of design abstraction from RTL to the behavior level (for example, refer to Patent Citation 1). In concrete terms, this is a method in which the operation of the LSI is described in a high level language such as the C language, and then is automatically converted to HDL source code at RTL using so called high level synthesis tool software. It is possible to enhance the productivity and the quality of the LSI design task by designing at the behavior level using such a high level synthesis tool.
[Patent Citation 1]
Japanese Laid-Open Patent Publication 2007-42085.